1. Field of the Invention
This invention relates to the field of electronic circuit design and, more particularly, to testing and verifying electronic circuit designs having one or more bus interconnects.
2. Description of the Related Art
The design of an electrical circuit, and particularly a programmable logic device (PLD), involves a significant amount of testing and verification to ensure that the resulting circuit functions within expected tolerances. Typically, a PLD is specified and designed using a hardware description language (HDL). When a circuit such as a PLD is to include a bus interconnect, testing and verification become even more complex.
In general, PLD designs including bus interconnects are tested using one of two different techniques. The first is to create a test bench, also referred to as a verification environment. A test bench refers to HDL descriptions that specify and verify the behavior of the electrical circuit. Generating a test bench involves describing the connections, events, and test vectors for different combinations of bus transactions. Events and data in electrical circuits are routinely described by signals, which are one bit wide, and vectors, which are two or more bits wide.
An HDL simulator is used to execute the test bench so that changes to signals and vectors over time can be observed. The simulator allows developers to visualize the logical and physical conditions that influence the behavior of the PLD. The simulator effectively tests the various logical and physical conditions that influence the behavior and proper functioning of the circuit.
Test benches are manually coded by a developer. Accordingly, despite the simulation benefits, test bench development tends to be a time consuming and error-prone process. Further, as the circuit design continues to evolve, the test bench also must be modified in accordance with the changes to the circuit design. In consequence, the maintenance of a test bench can be as time consuming and tedious a process as first developing the test bench.
The second technique for testing a PLD having a bus interconnect has been to create a larger system with other “known-to-work” components. Components that have already been tested and verified can be incorporated into a PLD design and configured to create or respond to bus transactions thereby interacting with bused components of the design. This solution, however, also has disadvantages.
In particular, using known-to-work components requires not only describing the connections of the bused components, but also programming the known components that will interact with the bused components. Essentially, developers must recreate the known components within a third-party development environment that is specifically tailored for testing bused components. The known components are reprogrammed within the third-party development environment to generate desired transactions and to respond to transactions originating from the bused components. This process also involves manually creating, compiling, and storing code so that components can access the code during execution to generate appropriate responses.
It would be beneficial to have an architecture and methodology that is less susceptible to error and overcomes the disadvantages described above.